Comparison of integrated LNA-MIXER Topologies for Wimax applications in a standard 90-NM CMOS process

Michael Angelo G. Lorenzo

(MS Graduated: 2nd Sem 2010-2011)

Abstract

There has been continued advancement in CMOS scaling through the years driven by the demand for higher performance in digital computation and memory. CMOS remains to be the predominant technology for digital circuits due to its low static power dissipation and excellent scalability. The shrinking of devices and increase in frequency of operation with scaling has driven the packing of more logic functionality in a smaller area. Also, the cost effectivity of integrating in a single system the analog, digital, mixed-signal, RF, and power management circuits has made system-on-a-chip implementation popular for electronic systems. With this, there is a need to evaluate the performance of RF circuits especially in nano-CMOS.

The focus of this research is on the RF receiver front-end circuits composed of the low-noise amplifier (LNA) and mixer. The front-end ensures the proper selection, amplification, and frequency translation of the input signals coming from the antenna of the receiver. Three LNA circuits, three mixer circuits, and nine integrated LNA-mixer circuits were designed and implemented in 90nm CMOS; all operating with a 1-V supply voltage. The three LNA topologies are: 1) cascaded common-source LNA 2) folded cascade LNA, and 3) shunt feedback LNA. The three mixer topologies are: 1) the single-balanced mixer 2) the double-balanced mixer, 3) and the dual-gate mixer. The nine front-end topologies were derived from the different combinations formed by integrating the three LNA topologies with the three mixer topologies. The receiver front-end topologies were designed for the target application of 5.8 GHz WiMAX. Simulation results show that out of the three LNA topologies, the cascaded common-source LNA had the best performance in terms of the adopted figure-of-merit. With 13.8 dB power gain, 1.7 dB noise figure and -6.63 dBm input-referred third-order intercept point (HP3), the cascaded common-source LNA was able to meet most of the LNA requirements for the WiMAX receiver and its performance was comparable to published 90nm LNA in CMOS. For the implemented mixer topologies, the double-balanced mixer had the best performance based on the adopted figure-of-merit for the mixers. It achieved 5.28 dB of conversion gain, 11.36dB of noise figure (@10MHz), and IIP3 of -1 dBm. Limitation in the available equipment for on-wafer measurement prevented the fabrication of this topology. The single-balanced mixer, which is next to the double-balanced mixer in terms of performance, was fabricated instead. The modularized design of the LNA and mixer circuits meant that the implementation of the front-end was achieved with the simple cascading of the LNA and mixer block. Thus, it has been shown that the performance parameters of the integrated LNA-mixer circuits have strong dependence on the parameters of the individual LNA and mixer blocks. Consequently, the cascaded common-source LNA integrated with the double-balanced mixer achieved the best performance among the nine front-end topologies with 21.94 dB gain, 1.68 dB noise figure (@10MHz), and -18.6 dBm IIP3.

Results from on-wafer DC test measurements show good agreement between the drawn supply current versus input bias voltage of the simulated and actual mixer circuit. DC measurements of the current drawn from the supply for the LNA chip, and consequently for the integrated LNA-mixer chip, differ by a substantial amount when compared to simulations and the difference increases as the input voltage bias increases. S-parameter measurements of the actual LNA shows a decreased forward gain which is the direct effect of the decrease in the transconductance of the transistor brought about by the decrease of bias current. The measured input and output return losses were also less compared to simulation results which is a possible result of the incompatibility of the GS probes used in the measurement. The results of the linearity measurements on the actual LNA chip showed higher values compared to simulations. The increased linearity is the result of the decrease in the LNA’s gain. An error causing the destruction of the actual mixer circuits during measurements prevented the extraction of the conversion gain of the mixer. An estimation of the conversion gain of the mixer was obtained based on the power gain of the LNA and the integrated LNA-mixer. The measured power gain of the integrated LNA-mixer was less than the simulated power gain which is a result of the reduction in power gain of the LNA and the mixer block comprising the front-end. The performance of the front-end is heavily dependent on the values of the active and passive components used. The limitations of the models, which can’t accommodate all the parasitics from the layout and short channel effects acquired with the use of short-channel devices, used during simulation have hindered the actual fabricated.